Elbrus 2000
The Elbrus 2000, E2K (Russian: Эльбрус 2000) is a Russian 512-bit wide VLIW microprocessor developed by Moscow Center of SPARC Technologies (MCST) and fabricated by TSMC.
It supports 2 instruction set architecture (ISA):
Thanks to its unique architecture Elbrus 2000 can execute up to 23 instructions per clock so even with its modest clock speed can compete with much faster clocked superscalar microprocessors especially when running in native VLIW mode.
Supported operating systems
Elbrus 2000 Highlights
| produced |
2005 |
| process |
CMOS 0.13 µm |
| clock rate |
300 MHz |
| peak performance |
- 64 Bit: 5.8 GIPS
- 32 Bit: 9.5 GIPS
- 16 Bit: 12.3 GIPS
- 8 Bit: 22.6 GIPS
|
| data format |
- integer: 32, 64
- float: 32, 64, 80
|
| cache |
- 64 KB L1 instruction cache
- 64 KB L1 data cache
- 256 KB L2 cache
|
| data transfer rate |
- to cache: 9.6 GByte/s
- to main memory: 4.8 GByte/s
|
| transistors |
75.8 million |
| connection layers |
8 |
| packing / pins |
HFCBGA / 900 |
| chip size |
31×31×2.5 mm |
| voltage |
1.05 / 3.3 V |
| power consumption |
6 W |
External links